Unless otherwise indicated herein, the materials described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section.
Various components of a traditional computer system may be integrated into a single integrated circuit (IC). The IC may comprise several regions that are each dedicated to a specific functionality, such as a memory controller (MC) region and a double data rate (DDR) input/output (I/O) region. Data may be transmitted from the MC region to the DDR I/O region via, for example, flip-flop based FIFOs or shift registers. The two regions may operate under the same clock frequency. However, for various reasons, the clocks of the two regions may originate from different clock sources, e.g., different Phase Locked Loop (PLL) clock sources. Under certain circumstances, the clock skews between the two regions may be greater than 50% of each clock cycle. In order to accommodate the clock skew, additional setup and hold time tolerance may be required for the flip-flop based FIFOs to transfer data between the two regions in a consistent manner. The increased setup and hold timing requirements may cause extra delay in the path of data transmission, which may be undesirable, especially if the data transmission between the two regions is latency critical.
Furthermore, the two regions of the IC may operate under different voltage levels. As such, data may need to be level-shifted after entering the receiving region. Level-shifting the data using separate circuit blocks may further increase the delay.